Sunday, March 31, 2019

User Interfaces Ic Compiler Computer Science Essay

go forr Interfaces Ic compiler Computer Science EssayIC compiler is the softw be package from Synopsys for Physical image of ASIC. It provides necessary machines to breeze through the back end excogitate of the very deep submicron physiques. The inputs to the IC compiling program be a gate-level pelflist which give the bounce be from DC compiling program or third-party tools, a detailed floor innovation which raise be from previous designing imagening through IC compiler or early(a) third-party tools, timing constraints and other constraints, animal(prenominal) and timing libraries provided by manufacturer, and foundry-process entropy. IC compiler generates a GDSII-format filing cabinet as payoff ready for tape out of the deterrent. In summateition, it is likely to export a throw Exchange Format (DEF) commit of primed(p) netlist data ready for a third-party router. IC compiler personas a binary program Synopsys Milky fashion database, which roll in the hay be apply by other Synopsys tools based on Milkyway. 164.2 User InterfacesIC Compiler jakes be utilise both with shield interface (icc_shell) or with Graphical substance ab phthisisr interface (graphical expenditurer interface). Shell interface is the argument-line interface, which is employ for batch mode, scripts, ty betoken flagg ascendences, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical summary and visible editing tool. authoritative tasks, much(prenominal) as very accurately displaying the intent and providing visual psycho abridgment tools, brush off only bring to passed from the GUI. Also tool check language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts.The IC Compiler visualise guide is an easy-to-use, single-pass flow that provides convergent timing colony. Figure 4.1 shows the basic IC Compiler physi que flow, which is centered about three nucleus dominates that answer position and optimization ( set out_opt), measure tree diagram tax write-off and optimization (clock_opt), and routing and postroute optimization (route_opt). 16icc1Figure 4.1 IC Compiler Design Flow 21For most sees, if the place_opt, clock_opt, and route_opt stairs are followed, IC Compiler will provide optimal essences. You can use IC Compiler to efficiently fulfil chip-level design supplying, posture, clock tree tax deduction and routing on designs with moderate timing and congestion ch everyenges.To further improve the prime(prenominal) of results for your design you can use additional commands and switches for placement, clock tree tax write-off, and routing go that IC Compiler provides.IC Compiler design flow involves slaying of following steps1. Set up and prepare the libraries and the design data.2. perpetrate design blueprintning and supply planning.-Design planning is to perform nec essary steps to stimulate a floorplan, gibe the sizing of the design, create the margin and affectionateness area, create site rows for the placement of standard cells, even out up the I/O pads.- function planning, is to perform necessary steps to create a forcefulness plan to meet the male monarch budget and the target flight current.3. coiffure placement and optimization.IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and disbands timing closure issues for the provided design. You can supply this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations.To perform placement and optimization, use the place_opt core command (or from GUI require Placement menu and then subject matter Placement and optimisation sub-menu).4. Perform clock tree synthesis and o ptimization.To perform the clock tree synthesis and optimization phase, use the command clock_opt (orchoose clock Core quantify Tree Synthesis and Optimization in the GUI).IC Compiler clock tree synthesis and embedded optimization solve perplex clock tree synthesis problems, such(prenominal) as blockage turning away and the correlation amidst preroute and postroute data. time tree optimization improves both clock skew and clock insertion wait by performing buffer zone sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy committal insertion, and balancing of interclock delays.5. Perform routing and postroute optimization.To perform routing and postroute optimization, use the route_opt core command (or choose Route Core Routing and Optimization in the GUI).As part of routing and postroute optimization, IC Compiler performs world-wide routing, detail routing, track assignment, topological optimization, and engine ering change order of battle (ECO) routing. For most designs, the default routing and postroute optimization tidy sumup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing therouting and postroute optimization functions for particular(prenominal) needs.6. Perform chip finishing and design for manufacturing tasks.IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the versatile stages of the design flow to address process design issues encountered during chip manufacturing.7. keep open the design.Save your design in the Milkyway format. This format is the interior database format used by IC Compiler to retention all the logical and physical tuition about a design. 164.3 How to Invoke the IC Compiler1. put down in to the UNIX environment with the user id and password .2. Start IC Compiler from the UNIX promtUNIX$ i cc_shellThe xterm unix prompt turns into the IC Compiler shell command prompt.3. Start the GUI.icc_shell start_guiThis windowpane can display schematics and logical browsers, among other things, once a design is loaded.4.4 Preparing the DesignIC Compiler uses a Milkyway design subroutine library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format.These steps are explained in the following sections background signal Up the Libraries Setting Up the position and show Nets look ating the Design An nonating the Physical Data Preparing for measure Analysis and RC Calculation Saving the Design4.4.1 Setting Up the LibrariesIC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries. Setting Up the Logic LibrariesIC Compiler uses logic libraries to provide timin g and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs.IC Compiler uses variables to define the logic library settings. In each session, you essential define the determine for the following variables (either interactively, in the .synopsys_dc.setup excite, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries search_pathLists the paths where IC Compiler can make up the logic libraries. target_libraryLists the logic libraries that IC Compiler can use to perform physical optimization. link_libraryLists the logic libraries that IC Compiler can search to resolve consultations. Setting Up the Physical LibrariesIC Compiler uses Milkyway reference libraries and engine room (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your engi ne room library. In addition, these reference libraries define the placement unit tile. The applied science files provide information such as the puddles and characteristics (physical and electrical) for each metal layer, which are technology-specific.The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains some(prenominal) views of the cell, which are used for divergent physical design tasks.If you have non already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it in advance working on your design.This section describes how to perform the following tasks Create a Milkyway design libraryTo create a Milkyway design library, use the create_mw_lib command (or choose data file Create Library in the GUI). Open a Milkyway design libraryTo open an existing Mil kyway design library, use the open_mw_lib command (or choose buck Open Library in the GUI). Report on a Milkyway design libraryTo report on the reference libraries given over to the design library, use the -mw_reference_library option.icc_shellreport_mw_lib-mw_reference_library design_library_nameTo report on the units used in the design library, use the report_units command.icc_shell report_units Change the physical library informationTo change the technology file, use the set_mw_technology_file command (or chooseFile Set Technology File in the GUI) to square off the new technology file name and the name of the design library. Save the physical library informationTo save the technology or reference control information in a file for afterwardward use, use thewrite_mw_lib_files command (or choose File Export issue Library File in the GUI). In a single magic trick of the command, you can output only one type of file. To output both a technology file and a reference control file, you must get by the command twice. Verifying Library ConsistencyConsistency between the logic library and the physical library is critical to achieving good results. forrader you process your design, ensure that your libraries are consistent by egestning the check_library command. 16icc_shell check_library4.4.2 Setting Up the situation and Ground NetsIC Compiler uses variables to define label for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets mw_logic0_netBy default, IC Compiler VSS as the ground net name. If you are using a different name,you must specify the name by setting the mw_logic0_net variable. mw_logic1_netBy default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable.4.4.3 rendering the DesignIC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format. Reading a Design in Milkyway Format Reading a Design in ASCII Format4.4.4 Annotating the Physical DataIC Compiler provides several methods of annotating physical data on the design Reading the physical data from a DEF fileTo read a DEF file, use the read_def command (or choose File Import Read DEF inthe GUI).icc_shell read_def -allow_physical design_name.def Reading the physical data from a floorplan fileA floorplan file is a file that you previously created by using the write_floorplancommand (or by choosing Floorplan Write Floorplan in the GUI).icc_shell read_floorplan floorplan_file_name counterparting the physical data from another designTo copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan Copy Floorplan in the GUI). 16icc_shell copy_floorplan -from design14.4.5 Preparing for Timi ng Analysis and RC CalculationIC Compiler provides RC computer science technology and timing analysis capabilities for bothpreroute and postroute data. Before you perform RC weighing and timing analysis, youmust fatten out the following tasks Set up the TLUPlus filesYou specify these files by using the set_tlu_plus_files command (or by choosing File Set TLU+ in the GUI).icc_shell set_tlu_plus_files -tech2itf_ mathematical function ./path/map_file_name.map -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/ take up_settings.tlup (Optional) Back-annotate delay or parasitic dataTo back-annotate the design with delay information provided in a model chequer Format (SDF) file, use the read_sdf command (or choose File Import Read SDF in the GUI).To remove annotated data from design, use the remove_annotations command. Set the timing constraintsAt a minimum, the timing constraints must contain a clock explanation for each clock signal, as well as input and output arrival ti mes for each I/O port. This requirement ensures that all signal paths are constrained for timing.To read a timing constraints file, use the read_sdc command (or choose File Import Read SDC in the GUI).icc_shell read_sdc -version 1.7 design_name.sdc train the analysis modeConditions such as fabrication process, operating temperature, and power supply potential drop can vary semiconductor device parameters. You can specify the operating conditions for analysis with the set_operating_conditions command. (Optional) Set the derating factorsIf your timing library does not include minimum and maximum timing data, you can perform synchronic minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors. Select the delay calculation algorithmBy default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. 164.4.6 Saving the DesignTo save the design in Milkyway format, use the save_mw_cel command (or choose File Save Design in the GUI). 16CHAPTER 5 Design Planning5.1 knowledgeabilityDesign planning in IC Compiler provides basic floorplanning and prototy marijuana cigaretteg capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and face plan conclaves, in-place optimization, prototype international routing analysis, hierarchical clock planning, performing nightfall assignment on sof t macros and plan groups, performing timing budgeting, converting the hierarchy, and meliorate the pin assignment. king net profit synthesis and power profits analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. federal agency network analysis validates the power synthesis results by performing voltage- cut and electromigration analysis. 16Figure 5.1 IC Compiler Design Planning 215.2 Tasks to be performed during Design Planning signizing the Floorplan Automating overstep sizing Exploration manipulation Black Boxes do an Initial Virtual tied(p) Placement Creating and organisation Plan Groups playing Power Planning playacting Prototype Global Routing playacting Hierarchical clock Planning do In-Place Optimization Performing Routing-Based Pin Assignment Performing RC Extraction Performing Timing Analysis Performing Timing Budgeting Committing the Physical Hierarchy better the Pin Assignment5.3 Initializing the FloorplanThe steps in signizing the floorplan are described below. Reading the I/O modestysTo load the top-level I/O pad and pin constraints, use the read_io_constraints command. Defining the Core and Placing the I/O PadsTo define the core and place the I/O pads and pins, use the signize_floorplan command. Creating Rectilinear-Shaped BlocksUse the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a decided set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape LTUX. Writing I/O Constraint InformationTo write top-level I/O pad or pin constraints, use the write_io_constraints command.Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing. Adding mobile phone RowsTo add cell rows, use the add_row command. Removing Cell RowsTo remove cell rows, use the cut_row command. Saving the Floorplan InformationTo save the floorplan information, use the write_floorplan command.Writing Floorplan Physical Constraints for Design Compiler Topographical TechnologyIC Compiler can now write out the floorplan physical constraints for Design CompilerTopographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax iswrite_physical_constraints -output output_file_name -port_side 16Figure 5.2 Floor Plan later on Initialization 215.4 Automating Die Size ExplorationThis section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, diesize for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage declivity requirements. The technology is structured into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view.5.5 Handling Black BoxesBlack boxes can be equal in the physical design as either soft or hard macros. A black box macro has a gobed height and width. A black box soft macro surface by area and utilization can be shaped to best fit the floorplan.To handle the black boxes run the following set of commands.set_fp_base_gateestimate_fp_black_boxesflatten_fp_black_boxescreate_fp_placementplace_fp_pinscreate_qtm_model qtm_bbset_qtm_technology -lib library_namecreate_qtm_port -type clock $portreport_qtm_modelwrite_qtm_model -format qtm_bbreport_timing qtm_bb5.6 Performing an Initial Virtual straight off PlacementThe initial realistic flat placement is very fast and is optimized for wire length, congestion, and timing.The way to perform an initial virt ual flat placement is described below. Evaluating Initial Hard Macro PlacementNo straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on virtual(a) design experience. Specifying Hard Macro Placement ConstraintsDifferent methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement.Creating a User-Defined Array of Hard MacrosSetting Floorplan Placement Constraints On Macro CellsPlacing a Macro Cell Relative to an Anchor ObjectUsing a Virtual Flat Placement StrategyEnhancing the Behavior of Virtual Flat Placement With the macros_on_edge SwitchCreating Macro Blockages for Hard Macros exaggerate the Hard Macros Padding the Hard MacrosTo avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined hyperbolize surmount or keepout margin around t he macros. One can set this padding distance on a selected macros cell instance master.During virtual flat placement no other cells will be displace within the specified distance from the macros edges. 16To set a padding distance (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. Placing Hard Macros and Standard CellsTo place the hard macros and standard cells simultaneously, use the create_fp_placement command. Performing Floorplan EditingIC Compiler performs the following floorplan editing operations.Creating objectsDeleting objectsUndoing and redoing edit changesMoving objectsever-changing the way objects snap to a gridAligning movable objects5.7 Creating and organisation Plan GroupsThis section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific section of the core area. This section also describes how to automatically place and sha pe objects in a design core, add padding around plan group boundaries, and proceed signal outflow and maintain signal oneness by adding modular block screen to plan groups and soft macros.The following steps are covered for Creating and Shaping Plan Groups. Creating Plan GroupsTo create a plan group, create_plan_groups command.To remove (delete) plan groups from the current design, use the remove_plan_groups command. Automatically Placing and Shaping Objects In a Design CorePlan groups are automatically shaped, sized, and placed inner the core area based on the dispersal of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed the other blocks, whether or not they are inside the core, are subject to being moved or reshaped.To automatically place and shape objects in the design core, shape_fp_blocks command. Adding Padding to Plan GroupsTo prevent congestion or DRC violations, one can add padding ar ound plan groupboundaries. Plan group padding sets placement blockages on the intimate and externaledges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding.To add padding to plan groups, create_fp_plan_group_padding command.To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. Adding Block Shielding to Plan Groups or Soft MacrosWhen two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the international of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro.To add block shielding for plan groups or soft macros, use the create_fp_block_shielding c ommand.To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. 165.8 Performing Power PlanningAfter completed the design planning process and have a complete floorplan, one can perform power planning, as explained below. Creating Logical Power and Ground ConnectionsTo define power and ground connections, use the connect_pg_nets command. Adding Power and Ground RingsIt is necessary to add power and ground rings aft(prenominal) doing floorplanning.To add power and ground rings, use the create_rectangular_rings command. Adding Power and Ground StrapsTo add power and ground straps, use the create_power_straps command. Prerouting Standard CellsTo preroute standard cells, use the preroute_standard_cells command. Performing Low-Power Planning for Multithreshold-CMOS DesignsOne can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to skip overall power consumption substantially becaus e it reduces leakage power as well as switching power. Performing Power Network SynthesisAs the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the policy change time needed to identify and fix power and signal integrity problems.By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing.To perform the PNS, one can run the set of following commands. 16synthesize_fp_ racewayset_fp_rail_constraintsset_fp_rail_constraints -set_ringset_fp_block_ring_constraintsset_fp_power_pad_constraintsset_fp_rail_region_constraintsset_fp_rail_voltage_area_constraintsset_fp_rail_strategy Committing the Power PlanOnce the IR drop map meets the IR drop constr aints, one can run the commit_fp_railcommand to transform the IR drop map into a power plan. Handling TLUPlus Models in Power Network SynthesisPower network synthesis supports TLUPlus models.set_fp_rail_strategy -use_tluplus true Checking Power Network Synthesis IntegrityInitially, when power network synthesis first proposes a power put away structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one aptitude discover problem areas in design as a result of automatic or manual cell placement. These areas are referred to as lamp chimney areas and pin connect areas.To Check the PNS Integrity one can run the following set of commands.set_fp_rail_strategy -pns_commit_check_fileset_fp_rail_strategy -pns_check_chimney_fileset_fp_rail_strategy -pns_check_chimney_file pns_chimney _reportset_fp_rail_strategy -pns_check_hor_chimney_layersset_fp_rail_strategy -pns_check_chimney_min_distset_fp_rail_strategy -pns_check_pad_connection file_nameset_fp_rail_strategy -pns_report_pad_connection_limitset_fp_rail_strategy -pns_report_min_pin_widthset_fp_rail_strategy -pns_check_hard_macro_connection file_nameset_fp_rail_strategy -pns_check_hard_macro_connection_limitset_fp_rail_strategy -pns_report_min_pin_width Analyzing the Power NetworkOne perform power network analysis to predict IR drop at different floorplan stages onboth complete and incomplete power nets in the design.To perform power network analysis, use the analyze_fp_rail command.To add virtual pads, use the create_fp_virtual_pad command.To turn off the hard macro blockages, use the set_fp_power_plan_constraints command. Viewing the Analysis ResultsWhen power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current tightness values to the database by saving the CEL view that has just been analyzed. Reporting Settings for Power Network Synthesis and Power Network Analysis StrategiesTo get a report of the current values of the strategies used by power network synthesisand power network analysis by using the report_fp_rail_strategy command. 165.9 Performing Prototype Global RoutingOne can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect contingent congestion hot spots that might exist in the floorplan payable to the placement of the hard macros or inadequate channel spacing.To perform global routing, use the route_fp_proto command.5.10 Performing Hierarchical Clock PlanningThis section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stage s of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design. Setting Clock Planning OptionsTo set clock planning options, use the set_fp_clock_plan_options command. Performing Clock Planning OperationsTo perform clock planning operations, use the compile_fp_clock_plan command. Generating Clock Tree ReportsTo generate clock tree reports, use the report_clock_tree command. Using Multivoltage Designs in Clock PlanningClock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas. Performing Plan Group-Aware Clock Tree Synthesis in Clock PlanningWith this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during naval division and budgeting. 165.11 Performing In-Place OptimizationIn-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed timing improvement, area recovery, and fixing DRC violations. These optimizations prese

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